This Application claims the benefit of Korean application no. 34290/1998 filed on Aug. 24, 1998, which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a liquid crystal display, and more particularly, to a gate driving circuit in a liquid crystal display.
2. Background of the Related Art
Referring to FIG. 1a, a liquid crystal display is, in general, provided with a liquid crystal panel 11, a driver unit 12 having a plurality of gate line drivers (GD) around the liquid crystal panel 11, and a source line driver unit 13 having a plurality of source line drivers (SD). As shown in FIG. 1b, the liquid crystal panel 11 is provided with a plurality of gate lines G1, G2, G3, - - - , Gn, a plurality of source lines S1, S2, S3, - - - , Sn in a direction crossing each of the gate lines, a thin film transistor 11a formed at a crossing point of the gate lines and the source lines, and a liquid crystal capacitor 11b connected to its respective thin film transistor 11a. 
In order to display an image on the liquid crystal display, after applying a driving signal to the gate lines in a sequence, a data signal is applied to the source lines, causing a change of the orientation of liquid crystal stored in the respective liquid crystal stored in the respective liquid crystal capacitors, thus displaying an image on the liquid crystal panel 11. The driving signal applied to the gate lines is provided from the gate line drivers GD. And, the data signal applied to the source lines is provided from the source line drivers SD. At least one gate line drivers GD and source line drivers SD are provided depending on the size of the liquid crystal panel.
FIG. 2 illustrates details of the gate line driver GD. The gate line driver GD includes a level changing unit 21, a shift registering unit 22, a level shifting unit 23, and a buffering unit 24. The level changing unit 21 changes a level VDL or VDD of an external signal into a level Vss or VDD required for the system operation. The shift registering unit 22 is provided with 154 shift registers SR1xcx9cSR154, each operative in response to a signal level changed by the level changing unit 21, for shifting a driving signal applied to the gate line in a sequence. The level shifting unit 23 is provided with 154 level shifters LS1xcx9cLS154, each for shifting a level of the driving signal from the shift registering unit 22 to a level Vss or VCOM.
The buffering unit 24 outputs signals out1xcx9cout154 which are applied to the gate lines in a sequence. For example, initially when the first buffer BF1 provides a high signal VCOM, the remaining buffers provide a low signal VL. Then, the buffering unit 24 is shifted, so that in this time, the second buffer BF2 provides a high signal, while the remaining buffers including the first buffer BF1 provide a low signal. Thus, the high signal is applied starting from the first buffer BF1 to the 154th buffer BF154 in a sequence for applying the high signal starting from the first gate line to the 154th gate line in the liquid crystal panel 11 in sequence.
The number of the gate line driver GD changes according to the size of the liquid crystal panel 11. For example, if four gate line drivers GD are provided, the number of the gate lines in the liquid crystal panel 11 will be 154xc3x974=616.
As shown in FIG. 2, each of the gate line driver GD applies a signal from the buffering unit 24 to the gate line with either a high or low signal depending on received signals STV1, STV2, CPV, and OE. The STV1 and the STV2 signals are shift data input/output signals, i.e., bidirectional signals. When an arbitrary one of the plurality of gate drivers completes providing all the 154 signals in sequence, the next one comes into operation. The STV1 signal is an operation signal provided to the forward gate line driver, and the STV2 is an operation signal provided to the backward gate line driver. Accordingly, upon receiving the STV1 signal, the arbitrary gate line driver provides the STV2 signal to the next gate line driver after applying a driving signal to the gate line. The CPV signal is a vertical shift clock signal and the OE signal is an output enable signal.
FIG. 3 illustrates the operation waveform diagram of the gate line driver. Referring to FIG. 3, the STV1 signal is provided at a first falling edge of the CPV signal (clock signal), shifted to the second shift register SR2 through the first shift register SR1, and passed through the first level shifter LS1 and the buffer BF1, to provide a high level out1 signal to be applied to the first gate line at a second rising edge of the CPV signal. Then, the signal shifted to the second shift register SR2 at the next falling edge of the CPV signal is shifted to the third shift register SR3, passed through the second level shifter LS2 and the second buffer BF2, and provides a high level out2 signal to the second gate line at a third rising edge of the CPV signal. Thus, out1 to out 154 signals are provided in sequence matched to the rising edges of the clock signal clk according to the foregoing method. After providing the signals out1 up to out154, the STV2, an operation signal for the next gate line driver, is provided. The STV2 signal, being equivalent of the STV1 signal for the next gate line driver, provides 154 signals in sequence as explained before.
FIG. 4 illustrates a conventional gate driver circuit. Referring to FIG. 4, the gate driver circuit is provided with a plurality of gate line drivers connected in series. A first gate line driver 41-1 is synchronous to a clock signal CPV and operative in response to a driving signal of the STV signal. The first gate line driver 41-1 provides a STV2 signal to a second gate line driver 41-2 at a moment its own 154th signal is provided. Accordingly, the second gate line driver 41-2 provides signals out1 to out 154 in succession as explained before. Then, the second gate line driver 41-2 provides a STV2 signal to a third gate line driver 41-3 at a moment its own 154th signal is provided. Thus, the plurality of gate line drivers connected in series in the conventional gate driving circuit are driven in succession.
With reference to the waveforms shown in FIG. 5, if one of the plurality of gate lines in the liquid crystal panel 11 is selected (i.e., a high signal is applied), other gate lines are applied with low signals. A driving signal (i.e., the high signal) applied to one of the gate lines is shifted in succession synchronous to every rising edge of the clock signal. Of the signals provided from the first gate line driver 41-1 in FIG. 4, when the signal out154 is provided, the STV2 signal is provided synchronized to the falling edge of the clock signal. The STV2, equivalent of the STV1 for the second gate line driver 41-2, causes the second gate line driver 41-2 to provide signals from out1 to out154 in succession. When all the gate line drivers complete all operation in succession, one image is displayed on the liquid crystal panel.
However, the conventional gate line driver circuit has the following problems. In the gate line driver circuit provided with the plurality of gate line drivers, all of the gate line drivers are provided with the clock signals continuously started from the driving of the first gate line driver until the driving of the last gate line driver. Accordingly, the unnecessary driving of gate line drivers due to unnecessary application of the clock signal causes an wasteful power consumption.
Accordingly, the present invention is directed to a gate driving circuit in a liquid crystal display that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a gate driving circuit in a liquid crystal display with minimized power consumption by eliminating the unnecessary drivings of gate line drivers.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the gate driving circuit of the present invention is to be used in a liquid crystal display having a liquid crystal panel with thin film transistors and pixel electrodes for displaying an image, a source driving circuit for applying a video data to a source line in the liquid crystal panel, and a gate driving circuit for applying a driving signal to a gate line in the thin film transistor. The gate driving circuit includes a plurality of gate line drivers connected in series for applying the driving signal to the gate line, and clock generation controlling units provided to correspond to the gate line drivers for controlling a timing of the clock signal to respective gate line drivers to control a driving timing of respective gate line drivers.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.